The present invention relates to a visual display, particularly though not exclusively for use with data processing apparatus.
Visual displays for data processing apparatus, such as computers, are normally of the cathode ray tube type. These generally have a depth of the order of their size dimension, which conventionally is their corner to corner or diagonal dimension. This depth can render them inconvenient in use. Recently, laptop computers have become increasingly widely used. These incorporate a xe2x80x9cflatxe2x80x9d screen display, usually of the liquid crystal type.
Proposals have been made to provide displays having flat screen cathode ray tubes. These are known as Spindt cathodes, after the inventor of U.S. Pat. No. 3,755,704. In this specification, they are referred to as field emission devices.
The object of the present invention is to provide an improved xe2x80x9cflatxe2x80x9d screen field emission visual display and an emission device for the display.
According to a first aspect of the invention there is provided a field effect emission device for a visual display comprising:
a substrate and
an emission layer on one face of the substrate, the emission layer having:
a multiplicity of emitters and gates, arranged as an array of emission pixels and
conductive connections in the emission layer to the emitters and the gates;
the substrate having:
conductive vias provided through the substrate or at least a front layer thereof to at least some of the said conductive connections in the emission layer for electrical connection to their emitters and gates.
We envisage that normally all of the conductive connections in the emission layer will have respective vias.
Provision of the conductive vias to the conductive connections in the emission layer provides direct contact to the connections and thus to the emitters and the gates. This has advantages in terms of the real time response of the emitters and gates to control signals. In other words, it provides for fast switching of the emitters and gates and thus sharp video characteristics.
Normally, the conductive connections will be emitter and gate lines to which the vias connect directly.
In preferred embodiments, each of the emitter and gate lines has a plurality of vias connected to it.
Whilst it is envisaged that some of the vias may connect to their lines at their ends; preferably the vias are provided within the body of emitters or the gates, that is with emitters or gates positioned on the lines to both sides of the position of the vias.
In accordance with an important feature of the invention, the drivers are mounted on the back face (the face opposite from the emitter face) of the substrate. Again, in combination with the vias through the substrate this enhances emission response.
It is envisaged that the substrate can have a single layer, with electrical connection tracks and preferably driver contact pads provided on its face opposite from the emission layer.
Normally, the substrate has at least one substrate layer additional to the front substrate layer,
the or each said additional substrate layer having conductive vias therethrough,
electrical interconnection tracks being provided at the interface(s) between the or each adjacent pair of substrate layers for electrical interconnection of the vias of the pair(s) of adjacent layers and
electrical connection tracks and preferably driver contact pads being provided on an outer face of a back one of the additional substrate layer(s) opposite from the front substrate layer.
This arrangement provides that the pitch of the gate and emitter lines can be progressively fanned out for connection to drivers.
Additionally, the field emission device will usually include at least one intermediate, additional substrate layer between the front and the back substrate layers.
The electrical interconnection tracks provided at the interface(s) between the or each adjacent pair of substrate layers can be provided on one only of the respective substrate layers at the interface(s), inter-layer contact being between vias of one layer and tracks of the other layer. Alternatively, the electrical interconnection tracks can be provided on both of the respective substrate layers at the interface(s), inter-layer contact being between tracks of one layer and tracks of the other layer.
Preferably, no gate line nor emitter line connection via is coincident, from the front substrate layer to the next, with a via in the next substrate layer
Preferably, the gate line and emitter line vias are arranged in at least the substrate layer having the emission layer in an array of aligned series of vias in two alternate orientations, both orientations being offset with respect to the emitter and gate line directions within the array, all the series are parallel to one or other of the orientations. The array of aligned series of vias can be a zig zag array with gaps between the zigs and the zags. In one particular arrangement, one of the alternate orientations is equal to the orientation of the aligned series, and alternate series of vias are not only parallel but themselves aligned.
The substrate is preferably of ceramic, conveniently of alumina to provide compatibility of thermal expansion with other components of the visual display, particularly a face plate. The vias are apertures in the substrate layers, which are filled with sintered metallic material.
At least some of the electrically conductive connections, lines, connection tracks and interconnection tracks are locally recessed into the material of the substrate layer(s). In particular, the emitter lines are preferably flush on their emission sides with the emission side of the substrate, with a planar dielectric layer separating the emission lines and the gates lines. Normally, a resistive layer will be provided on the emitter line side of the dielectric layer.
In one embodiment, the substrate includes additional vias and conductive tracks for providing electric connection through the substrate for phosphor excitation lines.
In accordance with a further preferred feature, the back face of the substrate has a peripheral metallic stripe for solder connection of the device into the visual display.
Further, power and signal supply tracks are preferably provided on the back surface of the back layer for powering the drivers and providing control signals to them.
Normally, the gates are circular apertures in the gate line stripes, with the emitters being pointed features projecting towards the gate apertures through voids in the dielectric layer.
According to a second aspect of the invention there is provided a visual display comprising:
a field emission device of the first aspect;
a glass face plate incorporating phosphor material selectively excitable by the emission device pixels; and
fused sealing material peripherally sealing the face plate to the emission device, whereby the face plate is parallelly spaced from the emission layer of the emission device and the space therebetween is evacuated.
It can be envisaged that the sealing material is interposed directly between the face plate and the emission device. However, it is preferred that the sealing material is provided on a wall interposed between the face plate and the emission device.
In the preferred embodiments, the visual display includes a carrier attached to the face of the emission device opposite from its emission layer.
The preferred arrangement is that the fused sealing material is provided on a peripheral wall which is sealed to the carrier and extends from it to the face plate or which forms one limb of the carrier which is of L-shaped cross-section and extends towards the face plate, the face plate being sealed to the wall by the fused sealing material and the emission device being sealingly attached to the carrier at the face of the emission device opposite from its emission layer.
Whilst the emission device may be secured to the carrier by means of adhesive, in the preferred embodiments, the device is soldered to the carrier.
Preferably, the emission device and the peripheral, carrier wall are complementarily shaped, for locating the emission device on the carrier. In one embodiment, the peripheral, carrier wall defines a space into which the emission device fits with negligible gap between the emission device and the wall. In another embodiment, the peripheral, carrier wall defines a space which is larger than the emission device, one of the wall and the emission device, preferably the latter, having projections for engaging with the other, for location of the emission device, a gap being present between the wall and the emission device between the projections.
Since the emission device will have electronic components soldered to it, the soldering of the carrier is preferably effected with high temperature solder. For this, mating portions of the device and the carrier are provided with complementary metallic tracks, to one of which the solder is preliminarily applied. The back layer of the ceramic substrate and the carrier can include metallic tracks also connected by high temperature solder for electric power and drive signal connection to the device. Alternatively to this, connectors may be attached directly to the ceramic substrate in the manner of the drivers to be described below.
The carrier is preferably of the same material as the ceramic substrate, particularly to provide a similar coefficient of thermal expansion. Further, the carrier is preferably of laminated construction. As an alternative, the carrier may be of high temperature plastics material.
The sealing means preferably comprises fused glass frit between the face plate and the carrier. The frit can have sloping sides. Conveniently this is provided by shaping it to a trapezoidal cross-section. The advantage of this shape is that it enables a gap at the frit to be bridged.
To support the face plate against collapse towards the emission device, an array of spacers is preferably provided between the face plate and the emission layer. Conveniently the spacers can be secured to the face plate. They may be of glass, ceramic or high temperature plastics material. Spacers may be provided peripherallyxe2x80x94of the phosphor material on the face plate and the emission array on the substratexe2x80x94or within the area of the phosphor material and the emission array, that is the active area of the visual display. Such spacers are referred to as xe2x80x9couter spacersxe2x80x9d and xe2x80x9cinner spacersxe2x80x9d respectively. Preferably, some at least of the outer spacers can carry contact tracks for the phosphor excitation lines, whereby the phosphor pixels can be excited by drivers carried on the emission device. Where the arrangement of the inner spacers causes them to attract electron flow from the emitters, the former may carry an electrical track, which has a voltage applied to it in use, causing the electrons to be repelled to continue towards the phosphor material. Preferably, the inner spacers are set in grooves in the emission layer and in a layer on the face plate including the phosphor material layer.
The inner spacers may extend across the full width of the active area. Alternatively, they may be provided as short lengths and/or crosses. Whilst it is possible that the inner spacers may be of a width to obscure one or more lines of emission pixels, the preferred inner spacers are thin in comparison with the pixel line spacing, whereby they do not interfere with any of the pixels. For this, they may also have a tapered cross-section, being thinner at their face plate edge. The outer spacers can be thicker, particularly where they are providing connection to the phosphor excitation lines.
For a small display, a single emission device only may be provided in the display. For larger displays, a plurality of laterally abutted emission devices may be provided, all mounted on a common carrier. Preferably, the emission devices are dimensioned at abutting edges for pixel alignment and at peripheral edges for abutment with the peripheral carrier wall. The carrier has additional members bridging the side members of the carrier. The emission devices are supported and sealed at abutting edges by the bridging members. The bridging members and the emission devices are provided with complementary solder contacts for providing electrical contact between the circuitry of the adjacent emission devices. Conveniently this is provided at local swellings in the width of the bridging members, with sealing solder tracks following the edges of the bridging members and the solder contacts being provided between the solder tracks.
Preferably, the visual display includes an activatable getter for final evacuation of the display. Conveniently, this is positioned in the emission-device/peripheral-carrier-wall gap.
According to a third aspect of the invention there is provided a method in the manufacture a field effect emission device of the first aspect of the invention, the method consisting in the steps of:
forming an array of via apertures in a substrate;
filling the via apertures with conductive material to form vias; and
forming on one face of the substrate a series of conductive connection lines for emitters of an emission layer to be produced on the said face of the substrate, the emission layer to have:
a multiplicity of emitters and gates, arranged as an array of emission pixels;
the vias and at least some of the conductive connections being so positioned as to interconnect.
In one alternative, the forming of the emitter lines and the gate lines on the substrate fills the respective via apertures with conductive material of the said lines. Then, preferably, electrical connection tracks are formed on the face of the substrate opposite from the emission layer, with the tracks being so positioned as to interconnect with respective vias, the formation of the tracks connecting them with the vias and the respective emitter and gate lines.
Alternatively, electrical connection tracks can be formed first on the face of the substrate opposite from the emission layer, the tracks being so positioned as to interconnect with respective vias, with the formation of the tracks filling the via apertures. The emitter and gate lines are then subsequently formed and connected by the vias so formed to the respective electrical connection tracks.
Whilst it is envisaged that the lattice of conductive emitter and gates lines may be placed on the ceramic substrate by sputtering or like method, preferably the electrical connection tracks and/or the emitter and gate lines are formed by screen printing; the substrate is formed by tape casting of ceramic material; and the via apertures are formed by stamping them in the tape cast ceramic material when in the green state. As an alternative to stamping, the substrate may be pierced by etching.
In one particular embodiment, the emitter lines in the case of the front substrate layer or electrical connection tracks in the case of other substrate layers are formed by screen printing onto a smooth release layer, the substrate is formed by tape casting ceramic material over the emitter lines, the via apertures are formed by stamping and filled by screen printing. This latter will normal include printing of electrical connection tracks for the other side of the substrate layer, but can include screen printing into via apertures only.
Preferably the substrate is compressed between platens to cause the electrical connection tracks to be flush with the surface of the ceramic substrate.
Where the substrate has one or more additional layers with vias and electrical connection tracks formed in like manner, the layers are preferably compressed together to form electrical contacts at interlayer interfaces before firing, preferably having first been individually flattened by compression.
Preferably, the top surface of the substrate is polished in preparation for deposition of emitters on the surface.
In one embodiment, after screen printing of the emitter lines with the emission layer in a xe2x80x9cgreen statexe2x80x9d, it is compressed between platens to press the emitter line stripes into the substrate. Next, the dielectric layer and the resistive layerxe2x80x94when providedxe2x80x94are added. Preferably these are spun on. Then the gate lines are screen printed on. The substrate has more than one layer and the layers are compressed together to form electrical contacts at interlayer interfaces before firing, preferably having first been individually flattened by compression. The compression together ensures electrical contact at the vias. The assembly is then fired at elevated temperature to sinter the materials of the substrate and the electrical components. After firing, the gates and dielectric layer openings are made by micro-machining. Then the emitters are electrolytically deposited and micro-machined.
According to a fourth aspect of the invention there is provided a substrate for a field effect emission device produced by the method of the third aspect of the invention.